1. Technical Field
The present invention relates in general to dynamic logic circuitry, and in particular to a method and system for initializing the threshold voltage of a transistor within a dynamic circuit during a transition from a passive to an active mode of operation. Still more particularly, the present invention relates to a method and system for discharging Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) body voltages to prevent MOSFET switching thresholds from becoming unacceptably low, thereby preventing the dynamic circuit from being unduly susceptible to noise upon initialization from a passive mode of operation.
2. Description of the Related Art
Complementary Metal Oxide Semiconductor (CMOS) gate circuits are known in the art. A conventional dynamic CMOS gate 100 is illustrated in FIG. 1A. Dynamic CMOS gate 100 consists of an N-type transistor logic structure 105 whose output node 102 is pre-charged to V.sub.dd 112 by a P-type transistor 104 and conditionally discharged by an N-type transistor 106 connected to V.sub.ss 110. A clock input 108 provides a single phase clock signal to P-type transistor 104 and N-type transistor 106. Consistent with standard dynamic logic principles, a "pre-charge" phase occurs within dynamic CMOS gate 100 when clock input 108 is at logic "0". During the pre-charge phase, the path to V.sub.ss 110 is open via N-type transistor 106. Alternating with the pre-charge phase, is the "evaluate" phase, during which the path to V.sub.ss 110 is closed via N-type transistor 106 when clock input 108 is at a logic "1". N-type transistor 106 therefore serves as a pull-down switch and is commonly referred to in the art as a "footed switch" or alternatively as a "ground switch". In the interest of clarity, a transistor that is configured within a dynamic circuit analogously to N-type transistor 106 will be referred to hereinafter as the "ground switch".
Referring now to FIG. 1B, a block diagram of a conventional row of domino logic circuitry is depicted. As illustrated, row 150 includes two domino logic circuits 152 and 154, which may implement the same or different logic functions. A problem arises however, when either or both clock inputs C1 164 and C2 162 into dynamic circuits 154 and 152 and input/output latches 156, 158, and 160, are temporarily disabled or held at a logical 0 for a prolonged period of time. Referring again to FIG. 1A, when clock input 108 is inactive for a relatively long period, the bodies of transistors within logic structure 105 become charged due to leakage currents. As a result, the threshold voltage (commonly known as the "switching threshold") of such charged devices drop to an unacceptably low level, thereby causing these devices to be unduly susceptible to noise.
It would therefore be desirable to be able to control the body voltage of transistors within a dynamic circuit in order to stabilize the switching thresholds of the transistors. Further, it would be desirable to apply a pre-charge input signal into a grounding switch within a dynamic logic circuit prior to the dynamic circuit being activated from a passive mode of operation, such that the threshold voltage levels within the dynamic circuit may be properly initialized.